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PartDateTitleStatus
AN1405ECL Clock Distribution Techniques 
AN1406Designing with PECL (ECL at +5.0V) 
AN1408Power Dissipation for Active SCSI Terminators 
AN1410Configuring and Applying the MC74HC4046A Phase-Locked Loop 
AN1500IEEE Std. 1149.1 Boundary Scan for H4C Arrays 
AN1502Embedded RAM BIST 
AN1503ECLinPS(tm) I/O SPICE Modelling Kit 
AN1504Metastability and the ECLinPS(tm) Family 
AN1508High Frequency Design Techniques and Guidelines for Bipolar Gate Arrays 
AN1509ASIC Clock Distribution using a Phase-Locked Loop (PLL) 
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